1. Field of the Invention
The present invention relates to the improvement of a method of manufacturing, from a semiconductor wafer, a dielectric substrate including insulated and separated island regions and to a method of manufacturing semiconductor elements from the dielectric substrate, so as to obtain a high yield.
2. Description of the Related Art
FIGS. 2A to 2E show a conventional manufacturing method in which oxide film 20 is formed on semiconductor wafer 10 and is patterned so as to form oxide film 22 having a grid-like pattern shown in (FIG. 1).
Referring to FIG. 2A, silicon oxide film 20 is formed on the upper surface and side surface of semiconductor wafer 10. After a grid-shaped mask is formed on the upper surface of film 20, silicon oxide film 22 is formed having a grid-like pattern by means of a patterning step such as a photoresist technique. Next, with oxide film 22 being used as a mask, anisotropic etching is performed to form separation grooves 30 in the form of a grid over the upper surface of the wafer (FIG. 2B), after which silicon oxide film 23 is made to grow on the surfaces of grooves 30. Thereafter, oxide film 22 and oxide film 23 are covered on the entire surface of wafer 10 (FIG. 2C). As shown in FIG. 2C, oxide films 22 and 23 are subsequently designated as being a single entity by means of numeral 24.
In the step shown in FIG. 2D, polycrystalline silicon layer 40, serving as a support layer, is formed on oxide film 24 by subjecting a silicon chloride or the like to a gas-phase growth reaction.
Thereafter, layer 40 is lapped to a plane indicted by line a--a', and a reference plane is produced. Then, wafer 10 is lapped from the bottom side to a plane indicated by line b--b'. The resultant structure has a predetermined thickness spanning a distance between line a--a' and line b--b'.
FIG. 2E shows the resultant dielectric substrate having a plurality of monocrystalline island regions 50. Regions 50 have a predetermined depth and are separated by oxide film 24 covering the surfaces of grooves 30 and by silicon polycrystalline layer 40.
In the case of the above conventional method, the entire upper surface of the wafer is subjected to patterning to form grid-shaped silicon oxide film 22. As a result, grooves 30 are formed over the entire surface of the wafer, and inevitably on the peripheral region of the wafer, as shown in FIG. 1. Some of grooves 30 on the peripheral region may have defective shape. If the wafer suffers shock during manufacture, defective portion 31 would likely be produced, as shown in FIG. 2B.
When silicon polycrystalline layer 40 is made to grow on the semiconductor wafer 10, the growth rate of the peripheral area of layer 40 becomes, for example, higher than that of the central area of layer 40, so that the peripheral area of layer 40 will be thicker than the central area thereof, as shown in FIG. 2D. It would be difficult to precisely determine a reference plane (indicated by line a--a') for grinding layer 40. If line a--a' is inclined with respect to the bottom surface of wafer 10, and if wafer 10 is lapped from the bottom side thereof up to line b--b' with an equal distance being kept between line a--a' and line b--b', the resultant dielectric insulated substrate would then include island regions 50 having non-uniform thickness. If semiconductor elements are formed on such island regions 50, the semiconductor elements would have different characteristics, resulting in a low yield of excellent semiconductor elements.